1. Field of the Invention
The present invention relates to a support apparatus for designing semiconductor packages, in particular, for designing wires that connect semiconductor chips to a lead frame.
2. Background Art
Japanese Patent Laid-open No. Hei 5-233760 discloses a layout editing apparatus that is used for designing a layout of semiconductor package. This apparatus determines connections between a semiconductor chip and a lead frame automatically, checks the connection in accordance with wiring rules, and outputs a drawing of layout for the semiconductor package if the connection is appropriate.
Japanese Patent Laid-open Nos. Hei 5-67679, Hei 4-346239, and Hei 4-236668 disclose designing systems that determine the wire connection between a chip and leads while repeating verifications.
In recent years, as semiconductor packages have become denser, multichip packages wherein multiple semiconductor chips are contained in one package are being developed. In the multichip packages, wire-bonding technology is utilized not only for connections between the chips and a lead frame, but also for connections between the chips.
As apparent from the specifications and drawings of the above documents, the systems described above do not accommodate the design of the multichip packages since they determine and check the connections on the basis of two-dimensional design drawings. Therefore, when designing the multichip packages, it may be necessary to check the connections visually as required. However, this visual check may be burdensome for designers since in the multichip packages more wires are disposed in narrower regions than in the conventional packages.
An object of the present invention is to provide a support apparatus for designing multichip packages that assists designers to check wires connecting semiconductor chips to a lead frame.
The apparatus comprises verifying means to verify whether designed wires satisfy required conditions, on the basis of three-dimensional drawing data, rule data, and component data. The three-dimensional drawing data represents structure of the semiconductor device. The rule data defines the required conditions. The component data represents specifications of components of the semiconductor device.
The three-dimensional drawing data preferably represents a plurality of semiconductor chips to be mounted on the semiconductor devices; lead frames; and wires that connect the semiconductor chips to the lead frames as the components of the semiconductor devices.
The rule data preferably defines conditions of a positional relationship between each wire and each component that compose the semiconductor devices. The conditions determine, for example, the lower limit of a minimum distance between each wire and each component.
Each wire may be defined by three-dimensional coordinates of a point where the wire is connected to the semiconductor chip; three-dimensional coordinates of a point where the wire is connected to the lead frame; and geometry of loop of the wire. The geometry of the wire loop may be defined by a type of the wire loop and three-dimensional coordinates of characteristics by which the geometry of the wire loop is characterized.
The three-dimensional drawing data may include attribute data for identifying the components of the semiconductor devices. Then the verifying means may identify each component of the semiconductor devices on the basis of the attribute data.
The support apparatus may comprise a database for managing the three-dimensional drawing data, the rule data and the component data. In this case, the verifying means acquires each of the data from the database. In this case, the database may manage a plurality of selectable rule data. The verifying means uses one of the rule data indicated by input selection indicating information.
Other and further objects, features and advantages of the invention will appear more fully from the following description.